1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to a semiconductor package and corresponding process for fabricating the same.
2. Description of the Related Art
As is known in the electrical arts, conventional fan-out semiconductor packages typically comprises at least one conductive via formed within the package body of the package. In the manufacturing process for such semiconductor packages, the package body of the package is drilled through the use of a laser to form at least one via hole therein. This via hole is then plated and thereafter filled with conductive metals so as to form the conductive via. In conventional fan-out semiconductor packages, the package body is a composite material which includes epoxy resin and SiO2 fillers. Because the laser absorbability characteristics of the epoxy resin and SiO2 fillers are different, and the sizes of the SiO2 fillers typically vary from 10 to 100 μm, the circularity of the sidewall of the via hole is often poor, the surface roughness of sidewall of the hole is high, and the size of the hole is larger than optimal upon the completion of the aforementioned laser-drilling process. These particular deficiencies arise despite the use of high accuracy lasers for the drilling process. As a result, in the process of forming the conductive via as described above, the plating and subsequent hole-filling processes process are complex and time consuming which increases the associated costs, with the plating quality further being difficult to control.
More particularly, in conventional fan-out semiconductor packages, the plating of the via hole is facilitated through the use of a sputtering process. In the sputtering machine, the plating material is dispensed therefrom in a manner in which it enters a corresponding via hole in a direction which is generally parallel to the sidewall of the hole. This direction of entry into the hole, coupled with the extremely small particle sizes of the plating material being dispensed from the sputtering machine, often results in the fillers hindering the complete, uniform application of the plating layer to the sidewall. In this regard, the surface roughness of the sidewall of the hole is attributable to such sidewall being partially defined by portions of the fillers which protrude from the epoxy. Whereas the plating layer is typically applied to the top sides of the exposed fillers which face the sputtering machine, the opposite bottom sides of these fillers often have no plating layer applied thereto by the sputtering process. As a result, when a metal such as copper is ultimately filled into the hole to complete the formation of the conductive via, such metal material will easily adhere to the plating layer, but will not easily adhere to those areas of the sidewall (e.g., the undersides of the fillers) which do not have the plating layer applied thereto. This lack of adhesion typically results in the formation of voids, which could compromise the integrity of the conductive path defined by the via. Though the potential for such incomplete plating, and the resultant formation of voids, can be reduced by increasing the amount of material applied in (and thus the time taken to time to complete) the sputtering process, this gives rise to an undesirable increase in cost coupled with a decrease in productivity.
The present invention addresses and overcomes these deficiencies by providing a semiconductor device and corresponding process for fabricating the same wherein the semiconductor device includes at least one conductive via collectively defined by several materials of differing properties as optimizes both the manufacturability and functionality thereof. These, as well other features and advantages of the present invention, will be described in more detail below.